Universal Array platform shortens SoC turn-around times while partial frequency/voltage regulator technology reduces IC power consumption

Toshiba Corporation has announced two new system-on-chip (SoC) design platforms that address the critical design challenges facing developers of new and emerging multimedia ICs for mobile phones and other portable, battery-powered applications. The Universal Array platform significantly reduces the development time for media embedded processors, while the company’s ‘partial frequency/voltage regulator’ technology reduces system LSI power consumption during operation

Initially targeted at 130nm and 90nm process technologies, Toshiba’s Universal Array is a cost-effective solution that brings advanced flexibility to the SoC development and verification process. The result is dramatic reductions in turn-around-time for the production of engineering samples. The partial frequency/voltage regulator technology platform optimises the operating frequency and supply voltage at the module level. This allows developers to optimise the power consumption of each individual intellectual property (IP) block integrated into an SoC design, producing an overall decrease in IC power consumption.
All cell-based ICs must undergo a rigorous verification and testing process prior to production, a process that is as essential as it is time-consuming. Conventionally, once the design process reaches tape out, the point where EDA tools can be applied to production of engineering samples of ICs, the diffusion wafer (DW) that integrates the basic IC components is fabricated. The wafer then undergoes personalization (personalized wafer, PW) to complete the manufacturing process. Toshiba’s Universal Array shortens this process time by allowing fabrication of the DW at the same time as the implementation and timing verification processes.
As mobile multimedia SoC solutions advance in functionality and scale, measures to curb leakage current and power consumption are among the biggest challenges for system LSI engineers. Toshiba has already promoted a partial solution to this problem with the development and deployment of selective multi-threshold (MT) technology, which reduces leakage current and cuts standby power consumption. The partial frequency/voltage regulator platform complements this technology to reduce operating voltage. By integrating both selective MT technology and partial frequency/voltage regulator into SoC, Toshiba has realized an innovative SoC design platform for power management and transistor leakage control and it will apply the platform to future generations of devices. The end result will be seen in lower power consumption in mobile applications, such as cellular phones and digital still cameras.
Toshiba will apply Universal Array to the production of engineering samples of its TC280 series (130nm) devices in the first quarter of 2005 and plans to extend its application to the TC300 series (90nm) in the second quarter. The company has already used its partial frequency/voltage technology to achieve a 40 percent power saving on an operating module of a test chip (media embedded processor base) for mobile multimedia applications.
“Universal Array is a cost-effective solution that brings advanced flexibility to the SoC development and verification process,” said Takashi Yoshimori, Technology Executive of Toshiba’s Semiconductor Company. “This fast and flexible SoC development platform will allow us to offer customers faster turn around times and support them in responding to market needs with differentiated digital products.”
Commenting on the partial frequency/voltage regulator, he adds: “Development of this new technology really allows us to make an important contribution to overcoming power consumption limitations with a modular dynamic-voltage and frequency scaling architecture. Once we have made this new design platform a standard part of our low power design methodology, we will be able to offer improved device performance to our customers.”